1st Semester Grades, SY 2008-2009

EE 177 Sections IJK, IJK1, MN and MN1 [View]

EE 173-Lab Sections ABC, ABC1 and JP [View]

EE 177/EE 173 Diagnostic Exam

Your diagnostic exam schedules are as follows:

October 21 @ 2pm - for EE 177 students
October 21 @ 3pm - for EE 173 students

The exam would be good for 1 hour only. Students who both have EE177/173 subjects would take the exam at 2PM.

Basic concepts of VHDL would be covered on the exam like:
a. Creation of entity-architecture pair
b. Creation of components
c. Use of process blocks
d. Basic VHDL syntax
e. Use of signals and variables

You might be ask in the exam to create a basic VHDL code (entity-architecture pair code) out from a given problem. Problems to be given would be as simple as an adder/subtractor circuits and other simple combinational circuits. Objective question would might as well be given.

This is a requirement item for your laboratory.

Finals Exam for EE177

Our finals exam is scheduled on the posted date below:
October 20, 2008 - from 1:30-4:30 @ COE Amphi.

Coverage of the Exam
1. Memory Basics [download ppt slides here]
Exam type: Objective with discussion type question.
Level: Easy

2. Sequential Circuit Design
Exam type: Complete SC design using JK, D, or T-flip flop starting from formulating the state table up to coming up with its logic circuit diagram. 2 possible questions would come from this item.
Level: Average-Difficult

3. Combinational Circuit Design
Exam type: Complete CC design with advance circuits. Problems would be possible applications to Chapters 1-3 concepts of our textbook. 2 possible questions would come from this item.
Level: Average-Difficult

If you are looking for a removal on this course, this could be your chance in coming up with a good outcome in the exam to pass the course. But it's not a total guarantee that by merely passing this exam, you will pass the entire course. Stamp your class!

God Bless!

EE 177 Lecture Slides

Memory Basics powerpoint slides -[Download]

Deadlines

Here are the following deadlines for our ALU lab.

October 10 (Friday) - Barrel Shifter [SLL, SRL]
October 14 (Tuesday) - The complete ALU project.

Submissions will be on a hard copy.

Here is an example of a top circuit of an ALU project. This might have some differences with our implementation. But in general, this could suffice to what we are working on. Download here.

NO CLASSES

There will be no classes for my thursday (Oct. 2) and friday (Oct. 3) EE177 sections. I will be attending the funeral of my father at Bato, Plaridel, Misamis Occidental.

Laboratories for EE177/173 will continue till the next week.

EE177 Quiz slides

http://stephen562001.googlepages.com/Quiz6.pdf

On Barrel Shifter

Here's a document about the Barrel Shifter [download].

Please correct the number of stages that the Barrel Shifter have, which is 5 as printed in the manual, by changing it to three. Just read the downloadable document given above for additional information.

Lab announcement

September 22, 2008 (Monday)
EE 173 (ABC,ABC1,JP)/EE 177(MN, MN1) Lab Students
For those who have submitted their Worksheet last Friday, you may get them on my table tomorrow (Tuesday) from 10:30am-3pm. It will be used again when you submit the remaining 4 functions/operations of our ALU.

Instructions for everyone:
There is a modification for the Logical operations implementation. Instead of using directly the “AND” and “OR” operations (e.g. c <= a AND b), please implement something like this:
For the AND (this is just an example)
If a = ‘1’ then
if b = ‘1’ then
c <= ‘1’;
else
c<= ‘0’
end if;
else
c<= ‘0’;
end if;

For the OR
If a = ‘1’ then
c <= ‘1’;
elsif b = ‘1’ then
c <= ‘1’;
else
c<= ‘0’;
end if;


For those who have implemented their logic operations in this manner or similar to this, you don’t need to change them.

Visit often this site for further info regarding our lab.

EE 173/EE 177Lab Students

You should submit your lab worksheet until 2pm today, and you have two ways of submitting your VHDL code (for the 4 out of 8 functions required):

1. Email the codes to stephenhaim(at)yahoo(dot)com(dot)ph

Follow the instructions below:

a. Compress your files (the whole project folder) to a zip file and attached it in your mail.

b. In the Mail’s Subject, follow this format:

For EE 177

EE177- section-Lab5:LastName-FirstName

For EE 173

EE173- section –Lab4:LastName-FirstName

Emails should be sent not later than 5pm, today

2. Submit a hardcopy of your codes on my desk, not later than 5pm, today.

The lab worksheets will be returned back to you on Monday. 

THIS IS FOR STUDENTS WHO HAVEN’T YET SUBMITTED THEIR FIRST 4 OF 8 FUNCTIONS

EE 177 and EE 173 Diagnostic Exam

This October, before our lab ends, we will have a diagnostic exam on VHDL as our last activity. It would cover basic Logic circuit construction using VHDL, that is simple task like creating a basic entity-architecture description would be given.

EE177: LabFive -- Available

Your labFive is now available.
See this link for further details.

EE 173 : LabFour Available

Your Fourth Lab activity is now available. As discussed in the class, you are tasked to come up with the ALU, as specified. Please read the activity manual for more details.

Files
[1] LabFour Manual
[2] LabFour Worksheet

Deadline
The deadline for this lab is distributed as follows:
First Week(7 days after this lab is given to you) - submit a partial implementation of the ALU with 4 out of the 8 functions/operations being describe. You can choose any operations which you will solve first.
Second Week - submit the remaining four operations.
Third Week - submit the overall ALU system.

Important
For students who have EE173 concurrently and are under me in their EE177 lab, please approach me for another lab activity to comply.

EE 177 Lecture Notes

Here are the lecture notes that we will use in our class discussion. Please study them in advance.

1. http://stephen562001.googlepages.com/Chapter5.pdf
2.a http://stephen562001.googlepages.com/LCDF4_Chap_05_P1.ppt
b. http://stephen562001.googlepages.com/LCDF4_Chap_05_P2.ppt
c. http://stephen562001.googlepages.com/LCDF4_Chap_05_P3.ppt
3. http://stephen562001.googlepages.com/lec05-6-Seq.ppt

Tutorial
Questions: http://stephen562001.googlepages.com/tutSequential.pdf
Solutions:http://stephen562001.googlepages.com/tutSequentialsol.pdf

EE 177and EE173 Labs

I will provide you for now reading materials in VHDL to enhance further your knowledge on the subject. It would be beneficial if you practice more also.

Here are some lecture notes forVHDL:
VHDL Tutorial
VHDL lecture

Other VHDL resources:
http://sites.google.com/site/ee177laboratory/Home/resources-1

Before the end of the semester, I would give a short exam on VHDL.

(Your lab manuals are yet to be completed by me, so keep posted)

EE 173 Classes: Postponed

Instead of having classes this week, I will leave some notes for you to study and let's have our meeting postponed and we will meet probably next week.

Study on downloading VHDL programs in a SPARTAN 3E Starter Kit.

Take notice of additional activities I will be posting this week.
For your guidance.

EE 173: Classes

For the Monday, Wednesday & Thursday classes of EE 173 lab, we will meet next week on our scheduled lab class (September 1, 3 and 4, respectively).

Read notes on VHDL in sequential circuits.

Attendance will be checked.

EE177: LabFour -- Available

Your labFour is now available.
See http://sites.google.com/site/ee177laboratory/Home/laboratory-activities/labfour-blinking-leds for further details.

VHDL Testbench Generator

After writing an VHDL model the designer must
write a VHDL testbench to simulate the module.

The designer should use his time for thinking
about the design verification and not for writing
the VHDL testbench template.

So we decided to write a C-program which
generates such a template file.

The program needs a correct VHDL entity, reads
the entity information (ports, generics, ...) and then
generates the testbench using our Style Guide. .

Everyone knows that it is horrible to parse VHDL
so we don't support the following features:
- Type-, Subtype- and Subprogramdefinitions in
the entity section
- Keyword 'signal' in PORT and GENERIC declarations
- ??? (you can tell us, if you found one)

Here's the link: http://www.vhdl-online.de/TB-GEN/ent2tb1.htm

COPYRIGHT

Universität Erlangen-Nürnberg
Lehrstuhl für Rechnergestützten Schaltungsentwurf
Prof. Dr.-Ing. Wolfram H. Glauert
Paul-Gordan-Str. 5, 91052 Erlangen
Tel.: 09131-8523102
Fax: 09131-8523111
Email: vhdl@lrs.e-technik.uni-erlangen.de
W3: http://www.vhdl-online.de

EE 173: LabThree -- Available

Your next lab activity deals with the sequential logic circuit. This is a tutorial-type activity so there's no reason that you can't submit the deliverables on time.

Hardcopy version of this lab will not be provided. However, you can download its softcopy version thru this site. And also, I have disseminated to our lab workstations the files needed for the activity. Locate these files (which includes also the other 5 needed files below) at c:\ee173lab\labThree

Download:
EE173 LabThree
LabThree Worksheet A
LabThree Worksheet B (soon after LWA)

The following are the needed files for this activity:

1. top_sequence.vhd
2. sequence.vhd
3. sequence_tb.vhd
4. clockbuffer.vhd
5. top_sequence.ucf

Deliverables:

• LabThree Worksheet A
• LabThree Manual (one that contains the Intro, Objective, Process and the summarized steps of the implementation)
  

Date Due:
Monday Class - August 11, 2008 on or before 5pm
Wednesday Class - August 13 , 2008 on or before 5pm
Thursday Class - August 14 , 2008 on or before 5pm

*Late works will not be accepted

Additional Note:
This is a two-phase activity where the second phase involves the downloading of your project to the Spartan 3E board.

All Students - Re: Email Format

We will follow the format in submitting your source codes to my email.

In the Subject, please write the following:
for EE177: [EE177] - Lab No. - Name of Student
for EE173: [EE173] - Lab No. - Name of Student

Inside the body of your email:
Name
Section
Lab Title

Send to my email: stephenhaim(at)yahoo(dot)com(dot)ph

Note: only attach the main vhd file in your project (such as the testbench and other vhdl modules)

EE 177: LabThree -- Available

The third laboratory activity (LabThree: Introduction to Discrete Digital Logic and Programmable Logic) for EE177 is now available.

You may ask your Instructor for the hard copy version of the lab manual

Date due
For Tuesday Class - July 29
For Friday Class - August 1
---not later than 4:30pm

Download lab activity

Additional File:

• Testbench file

Further Readings:

• ISE In-Depth Tutorial
• ISE 8.2i Quick Start Tutorial
• VHDL Tutorial
  

EE 173: labTwo -- Available

Here is now the 2nd laboratory activity for EE173 students. Download your respective activity - for both beginners and advance type.

EE173 LabTwo (Beginners)
EE173 LabTwo (Advance)

Other Files
Appendix A
EE173 Lab Notebook Format


Be sure you download the correct lab activity. Those students who have taken EE177 in the previous semester(s) are considered advanced students.

Take notice on our lab notebook format above. See me in the office (Rm 201) if you have questions.

Date Due:
Monday Class - July 14, 2008 on or before 5pm
Wednesday Class - July 16, 2008 on or before 5pm
Thursday Class - July 17, 2008 on or before 5pm

*Late works will not be accepted

VHDL Modules

Here are 10 VHDL modules which could help deepen your understanding with VHDL. Each of the modules provides a detailed insight and example to some of the frequently used VHDL constructs.

Module 1
Module 2
Module 3
Module 4
Module 5
Module 6
Module 7
Module 8
Module 9
Module 10

Introduction To VHDL: Arrays, Operator, Functions, Procedures, Packages and Library

Arrays

type SHORT_WORD is array (15 downto 0) of bit
signal DATA_WORD: SHORT_WORD;
variable ALT_WORD: SHORT_WORD:= “01010101…”;
constant ONE_WORD: SHORT_WORD:= (others => ‘1’);

type matrix4x3 is array (1 to 4, 1 to 3) of integer;
variable matrixA: matrix4x3 := ((1, 2, 3), (4, 5, 6),
(7, 8, 9), (10, 11, 12));

type intvec is array (natural range <>) of integer;
signal intvec5: intvec (1 to 5) := (3, 2, 6, 8, 1);

---------------------------------------------------------
Operator

• Binary logical operatoors: and or nand nor xor xnor
• Relational operator: = /= < <= > >=
• Shift operator: sll srl sla sra rol ror
• Adding operators: + - &(concatenation)
• Unary sign operators: + -
• Multiplying operator: * / mod rem
• Miscellaneous operators: not abs **

---------------------------------------------------------
Functions

function function_name (formal-parameter-list)
return return-type is [declaration]
begin
sequential statements – must include return return-value;
end function-name;
The general form of a function call is
function_name (actual-parameter-list)

[loop-label:] for loop-index in range loop
sequential statements
end loop [loop-label];

---------------------------------------------------------
Procedures

procedure procedure_name (formal-parameter-list) is [declaration]
begin
sequential statements
end procedure-name;

procedure_name (actual-parameter-list);

---------------------------------------------------------
Packages And Library

package package_name is
package declarations
end [package][package_name];

package body package_name is
package body declarations
end [package body][package_name];

library, use
example: library BITLIB;
use BITLIB.bit_pack.all;

*identifiers in bold type denotes a VHDL keyword

Introduction To VHDL

VHDL Description Of Combinational Networks

Entity-Architecture Pairs
entity entity-name is
[port (interface-signal-declaration);]
end [entity] [entity-name];

architecture architecture-name of entity-name is
[declarations]
begin
architecture body
end [architecture] [architecture-name];

list-of interface-signals: mode type [:= initial–value]
{; list-of-interface-signals: mode type [:= initial-value]}

mode: in, out, inout (bidirectional)

Example
entity FullAdder is
port (X, Y, Cin: in bit;
Cout, Sum: out bit);
end FullAdder;

architecture Equation of FullAdder is
begin
Sum <= X xor Y xor Cin after 10ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end Equation;

--: Comment
<=: signal assignment.

VHDL Program Structure


Using VHDL Process

• process: a common way of modeling sequential logic in VHDL

process (sensitivity-list)
begin
sequential-statements
end process;

• if

if condition then
sequential statements
{elsif condition then sequential statements}
-- 0 or more elsif clauses may be included
[else sequential statements]
end if;

VHDL Models For A Multiplexer

• Conditional Assignment Statement
  F <= I0 when Sel = 0
  else I1 when Sel = 1
  else I2 when Sel = 2
  else I3;
  
  case Sel is
  when 0 => F <= I0; when 1 => F <= I1; when 2 => F <= I2; when 3 => F <= I3; end case;

Modeling A Sequential Machine

1. Behavioral Model
2. Data-flow Model
3. Structural Model

• wait-statement: uses instead of a sensitivity list.

wait on sensitivity-list;
wait for time-expression;
wait until boolean-expression;

Variables, Signals, And Constants
variable list_of variable_names : time_name [:= initial_value]
signal list_of_signal_name : type_name [:= initial_value]
constant constant_name : type_name := constant_value

--------------------------------------------------------
                  |  Locality
--------------------------------------------------------
variable   |  process, function, procedures
signal       |  architecture
constant  |  process, function, procedures, architecture
--------------------------------------------------------

type state_type is (S0, S1, S2, S3, S4, S5);
signal state : state_type : = S1;

*identifiers in bold type denotes a VHDL keyword

EE 173: labTwo -- update

Instead of giving you labTwo this time, I will just postpone it by giving the activity on our scheduled laboratory.

So for now, you just have to further acquaint yourselves and practice more on coding VHDLs.

Thanks.

VHDL Tutorial

Here's a VHDL Tutorial notes from Jan Van der Spiegel of the Department of Electrical Engineering, University of Pennsylvania.

• Download

EE 173: labTwo -- tomorrow

I haven't completed yet the instructions for labTwo today, so I will just post them here tomorrow, Thursday (June 26, 2008), in the afternoon.

Thanks.

VHDL Resources

Here are the first of a series of VHDL resources that you can download. These are PDF files so you need a PDF reader for these (Acrobat will do).

These are slides from Dr. Pong P. Chu, author of the book entitled "RTL Hardware Design Using VHDL"

[1] Introduction to Digital System Design
[2] Hardware Description Language
[3] Basic Language Constructs of VHDL
[4] Concurrent Signal Assignment Statements
[5] Sequential Statements
[6] Synthesis Of VHDL Code

Welcome

Welcome to the Introduction to FPGA-based Design using VHDL class.

This would be our online portal for our class, both for EE177 and EE173 labs. I will just make distinctions for specific instructions, notes for the two classes.

For EE177 class, each of the article header text would contain "EE177:" followed by the activity or note title. Example, for EE177 lecture one, I could have "EE177: Lecture 1". The same applies for EE177 class, modifying only EE177 to EE173.

This site would also served as an extension of our classroom. If I could find valuable resources, I would put them here too. So visit frequently here too.

You can reach me at stephenhaim[at]yahoo[dot]com[dot]ph. Please indicate your subject name (ee177 or ee173) in the Subject title of your mail.