EE 177/EE 173 Diagnostic Exam

Your diagnostic exam schedules are as follows:

October 21 @ 2pm - for EE 177 students
October 21 @ 3pm - for EE 173 students

The exam would be good for 1 hour only. Students who both have EE177/173 subjects would take the exam at 2PM.

Basic concepts of VHDL would be covered on the exam like:
a. Creation of entity-architecture pair
b. Creation of components
c. Use of process blocks
d. Basic VHDL syntax
e. Use of signals and variables

You might be ask in the exam to create a basic VHDL code (entity-architecture pair code) out from a given problem. Problems to be given would be as simple as an adder/subtractor circuits and other simple combinational circuits. Objective question would might as well be given.

This is a requirement item for your laboratory.