VHDL Testbench Generator

After writing an VHDL model the designer must
write a VHDL testbench to simulate the module.

The designer should use his time for thinking
about the design verification and not for writing
the VHDL testbench template.

So we decided to write a C-program which
generates such a template file.

The program needs a correct VHDL entity, reads
the entity information (ports, generics, ...) and then
generates the testbench using our Style Guide. .

Everyone knows that it is horrible to parse VHDL
so we don't support the following features:
- Type-, Subtype- and Subprogramdefinitions in
the entity section
- Keyword 'signal' in PORT and GENERIC declarations
- ??? (you can tell us, if you found one)

Here's the link: http://www.vhdl-online.de/TB-GEN/ent2tb1.htm

COPYRIGHT

Universität Erlangen-Nürnberg
Lehrstuhl für Rechnergestützten Schaltungsentwurf
Prof. Dr.-Ing. Wolfram H. Glauert
Paul-Gordan-Str. 5, 91052 Erlangen
Tel.: 09131-8523102
Fax: 09131-8523111
Email: vhdl@lrs.e-technik.uni-erlangen.de
W3: http://www.vhdl-online.de

EE 173: LabThree -- Available

Your next lab activity deals with the sequential logic circuit. This is a tutorial-type activity so there's no reason that you can't submit the deliverables on time.

Hardcopy version of this lab will not be provided. However, you can download its softcopy version thru this site. And also, I have disseminated to our lab workstations the files needed for the activity. Locate these files (which includes also the other 5 needed files below) at c:\ee173lab\labThree

Download:
EE173 LabThree
LabThree Worksheet A
LabThree Worksheet B (soon after LWA)

The following are the needed files for this activity:

1. top_sequence.vhd
2. sequence.vhd
3. sequence_tb.vhd
4. clockbuffer.vhd
5. top_sequence.ucf

Deliverables:

• LabThree Worksheet A
• LabThree Manual (one that contains the Intro, Objective, Process and the summarized steps of the implementation)
  

Date Due:
Monday Class - August 11, 2008 on or before 5pm
Wednesday Class - August 13 , 2008 on or before 5pm
Thursday Class - August 14 , 2008 on or before 5pm

*Late works will not be accepted

Additional Note:
This is a two-phase activity where the second phase involves the downloading of your project to the Spartan 3E board.

All Students - Re: Email Format

We will follow the format in submitting your source codes to my email.

In the Subject, please write the following:
for EE177: [EE177] - Lab No. - Name of Student
for EE173: [EE173] - Lab No. - Name of Student

Inside the body of your email:
Name
Section
Lab Title

Send to my email: stephenhaim(at)yahoo(dot)com(dot)ph

Note: only attach the main vhd file in your project (such as the testbench and other vhdl modules)

EE 177: LabThree -- Available

The third laboratory activity (LabThree: Introduction to Discrete Digital Logic and Programmable Logic) for EE177 is now available.

You may ask your Instructor for the hard copy version of the lab manual

Date due
For Tuesday Class - July 29
For Friday Class - August 1
---not later than 4:30pm

Download lab activity

Additional File:

• Testbench file

Further Readings:

• ISE In-Depth Tutorial
• ISE 8.2i Quick Start Tutorial
• VHDL Tutorial
  

EE 173: labTwo -- Available

Here is now the 2nd laboratory activity for EE173 students. Download your respective activity - for both beginners and advance type.

EE173 LabTwo (Beginners)
EE173 LabTwo (Advance)

Other Files
Appendix A
EE173 Lab Notebook Format


Be sure you download the correct lab activity. Those students who have taken EE177 in the previous semester(s) are considered advanced students.

Take notice on our lab notebook format above. See me in the office (Rm 201) if you have questions.

Date Due:
Monday Class - July 14, 2008 on or before 5pm
Wednesday Class - July 16, 2008 on or before 5pm
Thursday Class - July 17, 2008 on or before 5pm

*Late works will not be accepted

VHDL Modules

Here are 10 VHDL modules which could help deepen your understanding with VHDL. Each of the modules provides a detailed insight and example to some of the frequently used VHDL constructs.

Module 1
Module 2
Module 3
Module 4
Module 5
Module 6
Module 7
Module 8
Module 9
Module 10

Introduction To VHDL: Arrays, Operator, Functions, Procedures, Packages and Library

Arrays

type SHORT_WORD is array (15 downto 0) of bit
signal DATA_WORD: SHORT_WORD;
variable ALT_WORD: SHORT_WORD:= “01010101…”;
constant ONE_WORD: SHORT_WORD:= (others => ‘1’);

type matrix4x3 is array (1 to 4, 1 to 3) of integer;
variable matrixA: matrix4x3 := ((1, 2, 3), (4, 5, 6),
(7, 8, 9), (10, 11, 12));

type intvec is array (natural range <>) of integer;
signal intvec5: intvec (1 to 5) := (3, 2, 6, 8, 1);

---------------------------------------------------------
Operator

• Binary logical operatoors: and or nand nor xor xnor
• Relational operator: = /= < <= > >=
• Shift operator: sll srl sla sra rol ror
• Adding operators: + - &(concatenation)
• Unary sign operators: + -
• Multiplying operator: * / mod rem
• Miscellaneous operators: not abs **

---------------------------------------------------------
Functions

function function_name (formal-parameter-list)
return return-type is [declaration]
begin
sequential statements – must include return return-value;
end function-name;
The general form of a function call is
function_name (actual-parameter-list)

[loop-label:] for loop-index in range loop
sequential statements
end loop [loop-label];

---------------------------------------------------------
Procedures

procedure procedure_name (formal-parameter-list) is [declaration]
begin
sequential statements
end procedure-name;

procedure_name (actual-parameter-list);

---------------------------------------------------------
Packages And Library

package package_name is
package declarations
end [package][package_name];

package body package_name is
package body declarations
end [package body][package_name];

library, use
example: library BITLIB;
use BITLIB.bit_pack.all;

*identifiers in bold type denotes a VHDL keyword

Introduction To VHDL

VHDL Description Of Combinational Networks

Entity-Architecture Pairs
entity entity-name is
[port (interface-signal-declaration);]
end [entity] [entity-name];

architecture architecture-name of entity-name is
[declarations]
begin
architecture body
end [architecture] [architecture-name];

list-of interface-signals: mode type [:= initial–value]
{; list-of-interface-signals: mode type [:= initial-value]}

mode: in, out, inout (bidirectional)

Example
entity FullAdder is
port (X, Y, Cin: in bit;
Cout, Sum: out bit);
end FullAdder;

architecture Equation of FullAdder is
begin
Sum <= X xor Y xor Cin after 10ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end Equation;

--: Comment
<=: signal assignment.

VHDL Program Structure


Using VHDL Process

• process: a common way of modeling sequential logic in VHDL

process (sensitivity-list)
begin
sequential-statements
end process;

• if

if condition then
sequential statements
{elsif condition then sequential statements}
-- 0 or more elsif clauses may be included
[else sequential statements]
end if;

VHDL Models For A Multiplexer

• Conditional Assignment Statement
  F <= I0 when Sel = 0
  else I1 when Sel = 1
  else I2 when Sel = 2
  else I3;
  
  case Sel is
  when 0 => F <= I0; when 1 => F <= I1; when 2 => F <= I2; when 3 => F <= I3; end case;

Modeling A Sequential Machine

1. Behavioral Model
2. Data-flow Model
3. Structural Model

• wait-statement: uses instead of a sensitivity list.

wait on sensitivity-list;
wait for time-expression;
wait until boolean-expression;

Variables, Signals, And Constants
variable list_of variable_names : time_name [:= initial_value]
signal list_of_signal_name : type_name [:= initial_value]
constant constant_name : type_name := constant_value

--------------------------------------------------------
                  |  Locality
--------------------------------------------------------
variable   |  process, function, procedures
signal       |  architecture
constant  |  process, function, procedures, architecture
--------------------------------------------------------

type state_type is (S0, S1, S2, S3, S4, S5);
signal state : state_type : = S1;

*identifiers in bold type denotes a VHDL keyword