Introduction To VHDL

VHDL Description Of Combinational Networks

Entity-Architecture Pairs
entity entity-name is
[port (interface-signal-declaration);]
end [entity] [entity-name];

architecture architecture-name of entity-name is
[declarations]
begin
architecture body
end [architecture] [architecture-name];

list-of interface-signals: mode type [:= initial–value]
{; list-of-interface-signals: mode type [:= initial-value]}

mode: in, out, inout (bidirectional)

Example
entity FullAdder is
port (X, Y, Cin: in bit;
Cout, Sum: out bit);
end FullAdder;

architecture Equation of FullAdder is
begin
Sum <= X xor Y xor Cin after 10ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end Equation;

--: Comment
<=: signal assignment.

VHDL Program Structure


Using VHDL Process

• process: a common way of modeling sequential logic in VHDL

process (sensitivity-list)
begin
sequential-statements
end process;

• if

if condition then
sequential statements
{elsif condition then sequential statements}
-- 0 or more elsif clauses may be included
[else sequential statements]
end if;

VHDL Models For A Multiplexer

• Conditional Assignment Statement
  F <= I0 when Sel = 0
  else I1 when Sel = 1
  else I2 when Sel = 2
  else I3;
  
  case Sel is
  when 0 => F <= I0; when 1 => F <= I1; when 2 => F <= I2; when 3 => F <= I3; end case;

Modeling A Sequential Machine

1. Behavioral Model
2. Data-flow Model
3. Structural Model

• wait-statement: uses instead of a sensitivity list.

wait on sensitivity-list;
wait for time-expression;
wait until boolean-expression;

Variables, Signals, And Constants
variable list_of variable_names : time_name [:= initial_value]
signal list_of_signal_name : type_name [:= initial_value]
constant constant_name : type_name := constant_value

--------------------------------------------------------
                  |  Locality
--------------------------------------------------------
variable   |  process, function, procedures
signal       |  architecture
constant  |  process, function, procedures, architecture
--------------------------------------------------------

type state_type is (S0, S1, S2, S3, S4, S5);
signal state : state_type : = S1;

*identifiers in bold type denotes a VHDL keyword