Finals Exam for EE177

Our finals exam is scheduled on the posted date below:
October 20, 2008 - from 1:30-4:30 @ COE Amphi.

Coverage of the Exam
1. Memory Basics [download ppt slides here]
Exam type: Objective with discussion type question.
Level: Easy

2. Sequential Circuit Design
Exam type: Complete SC design using JK, D, or T-flip flop starting from formulating the state table up to coming up with its logic circuit diagram. 2 possible questions would come from this item.
Level: Average-Difficult

3. Combinational Circuit Design
Exam type: Complete CC design with advance circuits. Problems would be possible applications to Chapters 1-3 concepts of our textbook. 2 possible questions would come from this item.
Level: Average-Difficult

If you are looking for a removal on this course, this could be your chance in coming up with a good outcome in the exam to pass the course. But it's not a total guarantee that by merely passing this exam, you will pass the entire course. Stamp your class!

God Bless!