1st Semester Grades, SY 2008-2009

EE 177 Sections IJK, IJK1, MN and MN1 [View]

EE 173-Lab Sections ABC, ABC1 and JP [View]

EE 177/EE 173 Diagnostic Exam

Your diagnostic exam schedules are as follows:

October 21 @ 2pm - for EE 177 students
October 21 @ 3pm - for EE 173 students

The exam would be good for 1 hour only. Students who both have EE177/173 subjects would take the exam at 2PM.

Basic concepts of VHDL would be covered on the exam like:
a. Creation of entity-architecture pair
b. Creation of components
c. Use of process blocks
d. Basic VHDL syntax
e. Use of signals and variables

You might be ask in the exam to create a basic VHDL code (entity-architecture pair code) out from a given problem. Problems to be given would be as simple as an adder/subtractor circuits and other simple combinational circuits. Objective question would might as well be given.

This is a requirement item for your laboratory.

Finals Exam for EE177

Our finals exam is scheduled on the posted date below:
October 20, 2008 - from 1:30-4:30 @ COE Amphi.

Coverage of the Exam
1. Memory Basics [download ppt slides here]
Exam type: Objective with discussion type question.
Level: Easy

2. Sequential Circuit Design
Exam type: Complete SC design using JK, D, or T-flip flop starting from formulating the state table up to coming up with its logic circuit diagram. 2 possible questions would come from this item.
Level: Average-Difficult

3. Combinational Circuit Design
Exam type: Complete CC design with advance circuits. Problems would be possible applications to Chapters 1-3 concepts of our textbook. 2 possible questions would come from this item.
Level: Average-Difficult

If you are looking for a removal on this course, this could be your chance in coming up with a good outcome in the exam to pass the course. But it's not a total guarantee that by merely passing this exam, you will pass the entire course. Stamp your class!

God Bless!

EE 177 Lecture Slides

Memory Basics powerpoint slides -[Download]

Deadlines

Here are the following deadlines for our ALU lab.

October 10 (Friday) - Barrel Shifter [SLL, SRL]
October 14 (Tuesday) - The complete ALU project.

Submissions will be on a hard copy.

Here is an example of a top circuit of an ALU project. This might have some differences with our implementation. But in general, this could suffice to what we are working on. Download here.

NO CLASSES

There will be no classes for my thursday (Oct. 2) and friday (Oct. 3) EE177 sections. I will be attending the funeral of my father at Bato, Plaridel, Misamis Occidental.

Laboratories for EE177/173 will continue till the next week.

EE177 Quiz slides

http://stephen562001.googlepages.com/Quiz6.pdf